What is ABV ?

Modern SoC and ASIC design flow based on EDA tools have greatly enabled the handling of design complexity with the growing demands of various applications. One of the greatest challenges for the design teams is ensuring the functional correctness of the RTL design. Extensive verification is carried out to ensure that bugs are discovered early in the design flow as a bug discovered in post SoC fabrication testing would require costly silicon re-spin. However, there is an embedded goal in this challenge to shorten the verification cycle. New techniques are being researched to tackle the problem of test complexity by evolving the existing verification methodologies. Formal verification, an advancement over the conventional simulation based verification has been there for quite some time. The concept of property checking led to Assertion based verification which is a methodology used in functional property verification. It is aimed to improve the controllability and observability of deeply buried bugs in the design. It reduces the debugging time for the verification engineer and provides an integration path for more advanced forms of verification into the design flow.

Due to increase in complexity of the chip design, the verification time has increased significantly upto 70% of the overall chip design time.

For technologies in the sub-micron region, i.e. below 90nm the chip designing costs are enormous. Any bug or error found in the design post-fabrication could incur losses amounting to the entire budget allotted to the project.This discussion about formal verification brings about the need to describe a very closely related concept known as property checking and specification. Properties are simply statements of design intent i.e. statements showing the intended behavior of the design. They specify the correctness requirements of a design. An implementation of a property that is evaluated by the verification tool to validate the design intent is known as an assertion. In other words, assertions are statements about the design‘s behavior that need to be verified with the sole purpose of maintaining consistency between what the designer wants and what is being created. Therefore, statements of design intent are known as properties, and validation or verification of these statements is

done via assertions.

SOURCES:

1. H. D. Foster, "Trends in functional verification: A 2014 industry study," 2015 52nd     ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015, pp. 1-6.
2.  H. Foster, A. Krolnik, and D. Lacey, Assertion-Based Design, 2nd edn., Kluwer Academic     Publishers, Berlin, Germany, 2004.
3. Srikanth Vijayaraghavan, Meyyappan Ramanathan, A Practical Guide for System Verilog Assertions,   Springer, 2005.